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SN74HC373PWR
+BOMIC OCTAL TRANSP LATCH 20-TSSOP
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Nhà sản xuấtTexas Dụng cụ
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Ông. Phần #SN74HC373PWR
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Bảng dữ liệu SN74HC373PWR DataSheet
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Gói TSSOP-20
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Có sẵn4573
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Thông số kỹ thuật
| thuộc tính | Giá trị |
| Package / Case | Tape & Reel (TR),Cut Tape (CT) |
| Series | 74HC |
| Part Status | Active |
| Logic Type | D-Type Transparent Latch |
| Circuit | 8:8 |
| Output Type | Tri-State |
| Voltage - Supply | 2V ~ 6V |
| Independent Circuits | 1 |
| Delay Time - Propagation | 15ns |
| Current - Output High Low | 7.8mA, 7.8mA |
| Operating Temperature | -40°C ~ 85°C |
| Mounting Type | Surface Mount |
Tổng quan
Description
Key features include eight latches that are transparent in operation, meaning the outputs follow the data inputs when the latch enable (LE) is high. When LE is low, the latches store the data present at that instant. The outputs can be placed in a high-impedance state with the output enable (OE) control, allowing for bus-oriented applications. The chip is available in a TSSOP package, and its design ensures minimal power dissipation with typical propagation delays.
Common applications include data storage, data transfer, and bus interface in computing environments, where efficient and reliable data management is essential.
Equivalent
Features
1. Logic Family: High-speed CMOS (HC) with TTL-compatible inputs.
2. Function: Provides eight latches in a single package with the ability to store and buffer data.
3. Operating Voltage: Typically operates at 2V to 6V.
4. Output Type: 3-state outputs, allowing multiple devices to connect to a common bus.
5. Propagation Delay: Features fast propagation times, enhancing performance in high-speed applications.
6. Latch Enable and Output Control: Data inputs are transparent when the latch enable (LE) is high, and data is latched when LE is low. Outputs can be put into high-impedance state with an output control pin.
7. Package: Available in a TSSOP-20 package.
8. Power Consumption: Low power consumption due to CMOS technology.
9. Wide Temperature Range: Suitable for operation in various environments.
These features make the SN74HC373PWR ideal for applications requiring data storage, bus interfacing, and signal buffering.
Pinout
1. Latch Enable (LE): When this input is high, the data from the D input pins is transferred to the Q outputs. When it is low, the data is latched, or held, at the output regardless of changes at the D inputs.
2. Output Enable (OE): This control input enables or disables the output. When OE is low, the Q outputs reflect the state of the internal latches. When OE is high, the outputs are in the high-impedance state, effectively disconnecting them from the circuit.
3. Data Inputs (D0-D7): These are the data input pins. The data present on these pins is captured by the latches when LE is high.
4. Outputs (Q0-Q7): These are the data output pins, reflecting the state of the internal latches when OE is low.
This IC is often used in memory storage, buffering, and signal synchronization applications.