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SN74LVTH16374DLR
+BOMIC FF D-TYPE DOUBLE 8BIT 48SSOP
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Nhà sản xuấtTexas Dụng cụ
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Ông. Phần #SN74LVTH16374DLR
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Bảng dữ liệu SN74LVTH16374DLR DataSheet
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Thông số kỹ thuật
| thuộc tính | Giá trị |
| Series | 74LVTH |
| PartStatus | Active |
| BaseProductNumber | 74LVTH16374 |
| Function | Standard |
| Type | D-Type |
| OutputType | Tri-State, Non-Inverted |
| NumberofElements | 2 |
| NumberofBitsperElement | 8 |
| ClockFrequency | 160 MHz |
| MaxPropagationDelay@V,MaxCL | 4.5ns @ 3.3V, 50pF |
| TriggerType | Positive Edge |
| Current-OutputHigh,Low | 32mA, 64mA |
| Voltage-Supply | 2.7V ~ 3.6V |
| Current-Quiescent(Iq) | 190 µA |
| InputCapacitance | 3 pF |
| OperatingTemperature | -40°C ~ 85°C (TA) |
| MountingType | Surface Mount |
| SupplierDevicePackage | 48-SSOP |
| Package | 48-BSSOP (0.295", 7.50mm Width) |
| Packaging | Bulk, Tape & Reel (TR) |
Tổng quan
Description
Key points:
- 16-bit register with 3-state outputs
- Clock input and output-enable control
- Suitable for data buffering, bus isolation, and address/data interfacing
- Low-voltage CMOS (LV) device with TI’s standard timing characteristics
- Package: DLR suffix indicates RoHS-compliant small-outline (typical 20-pin) package
For exact pinout, electrical specs, timing diagrams, and Vcc range, consult the TI SN74LVTH16374 datasheet.
Equivalent
- MC74LVTH16374 — ON Semiconductor
- 74LVTH16374 — Nexperia (formerly Philips/NXP)
Note: packaging and suffixes vary; check exact data sheet and RoHS/packaging for your application.
Features
- 16-bit storage register with 3-state outputs
- Parallel data inputs (D0–D15) and parallel load capability
- Edge-triggered clock input for synchronous operation
- Asynchronous Master Reset (MR) to clear all bits
- Output Enable (OE) to place outputs in high-impedance state
- Very low-voltage operation: 1.65 V to 3.6 V
- CMOS technology: fast, low power
- Suitable for bus interfacing due to tri-state outputs
- Packaging: DLR (low-profile package variant)
Pinout
- Function: SN74LVTH16374DLR is an octal (8-bit) D-type transparent latch with 3-state outputs. It has eight data inputs (D0–D7), eight outputs (Q0–Q7), a latch-enable input (LE), and an output-enable input (OE). Data is latched when LE is active; outputs can be tri-stated when OE is active.
Manufacturer
- What kind of company: An American multinational that designs and manufactures semiconductors and integrated circuits (analog, digital, mixed-signal, embedded processing).
Application
- Buffering 16‑bit data/address buses between microprocessors/PLDs and memory or peripherals
- Shared bus driving with tri‑state enables to prevent contention
- Level shifting/isolation between voltage domains (e.g., 3.3V controller to 5V devices)
- I/O expansion and peripheral interfacing in embedded systems
- High‑speed data paths requiring buffering and impedance matching
- Signal‑integrity improvement on long lines or multi‑load nets
- Glue logic for memory, LCDs, and other controllers in MCU/FPGA design